High-Speed 64-Bit Binary Comparator using Three Stages with CMOS Logic Style

نویسندگان

  • Satyajit Anand
  • Mohamed I. Elmasry
  • Pierce Chuang
  • David Li
  • Manoj Sachdev
چکیده

High-speed 64-bit binary comparator using three stages with CMOS logic style is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator designs concentrating on delay. Means some modifications have been done in existing 64-bit binary comparator design to improve the speed of the circuit. Comparison between modified and existing 64-bit binary comparator designs is calculated by simulation that is performed at 90nm technology in Tanner EDA Tool.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

High-Speed 64-Bit Binary Comparator using Two Stages with Two Different Logic Styles

High-speed 64-bit binary comparator using two stages with two different logic styles is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comp...

متن کامل

A High-speed Tree-based 64-bit Cmos Binary Comparator

A high-speed tree-based 64-bit CMOS binary comparator is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator designs concentrating on...

متن کامل

High-Speed 64-Bit Binary Comparator using Two Different Logic Styles

High-speed 64-bit binary comparator using two different logic styles is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator designs c...

متن کامل

Design of High Speed Digital CMOS Comparator Using Parallel Prefix Tree

This paper Presents a new comparator design is proposed by using parallel prefix tree. Energy efficient and high speed operation of comparators is needed for high speed digital circuits. The comparison outcome of the most significant bit, proceeding bitwise toward the least significant bit only when the compared bits are equal. In existing system, the parallel prefix structure is designed for 1...

متن کامل

Design and Simulation of a 2GHz, 64×64 bit Arithmetic Logic Unit in 130nm CMOS Technology

The purpose of this paper is to design a 64×64 bit low power, low delay and high speed Arithmetic Logic Unit (ALU). Arithmetic Logic Unit performs arithmetic operation like addition, multiplication. Adders play important role in ALU. For designing adder, the combination of carry lookahead adder and carry select adder, also add-one circuit have been used to achieve high speed and low area. In mu...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2013